Timing recovery arrangements are necessary to compensate for the distorting effects of transmission channels on data pulse signals. One type of timing recovery unit presently in use comprises two subcircuits fabricated on a VLSI chip. One subcircuit is a clock recovery circuit and the other is a data pulse signal regenerating circuit; and the two subcircuits operate in parallel with each other. In operation the clock recovery circuit generates a clock pulse signal which is used to synchronize the operation of various circuits. The clock pulse signal is also used by the data regenerating circuit to mark the instant when a received data pulse signal is to be sampled.
During manufacture, it is very difficult to replicate subcircuits on many chips so that they all have identical electrical characteristics. Therefore, because of variations of the electrical characteristics of the subcircuits, each timing recovery arrangement must be tested. Frequently, manual adjustment of the timing recovery arrangement is required to provide an operable device. This testing procedure is both time-consuming and expensive. In some instances, where cost is a major factor, only those devices which meet specifications without adjustments are used.
In addition, temperature variations have an adverse effect on the operating characteristics of the two subcircuits. During the testing procedure, device performance is optimized at a single temperature. But, because performance degrades as the operating temperature in the field varies from the ideal temperature, devices are currently restricted to a relatively narrow commercial temperature range.
Clearly, an improved timing recovery arrangement is required.